Electronic packages (sometimes called modules) including semiconductor chips, especially high power chips, demand that heat from the chip be effectively dissipated away from the chip to the environment external of the package. The ability of the package to dissipate heat generated by the chip(s) is generally a function of the quality of the primary heat dissipation path from the chip to the external surface of the module. As is well known, inefficient heat escape can deleteriously affect the chip's operation and life.
In some known package designs, thermal paste or some other thermally conductive material is used as a type of interposer at a point in the primary heat dissipation path from the chip(s) to the package's external surface. Such paste is normally compliant in nature, thus presenting advantageous features. Some of these advantages include the ability to accommodate statistical variations in thickness of the chip(s) to be housed in the package, height of the chip's solder connections (in the case of the more advantageous “flip chip” packaging), cavity depth of the cooling structure, thickness of the seal (between the cooling structure, if bonded onto the package substrate), substrate camber, etc. The ability to control variations in the dimensions of such components is difficult, especially where the components come from different sources (vendors) or where reworking or modification of such components is required. This problem is especially apparent where large scale commercial production is involved. A compliant interposer helps considerably in this regard.
With respect to such heat dissipation paths, including those which utilize compliant pastes or the like, it is also known that the interposer or like component which forms the path from the chip(s) to the underside of the cooling structure may form the “weakest link” in the heat dissipation path; that is, interposers which use pastes or other materials may possess a lower thermal conductivity than other components of the heat dissipation path. It is essential, therefore, that any interfacing structure between chip and the cooling structure possess effective thermal conductivity, to thereby assure optimal heat escape for the sensitive chip.
Various examples of interposer structures are described in the following patents.
In U.S. Pat. No. 5,387,815, there is described a semiconductor chip module which includes a substrate on which a wiring portion is formed, a semiconductor chip mounted so as to face a circuit side down to the wiring portion, a heat sink with one end in contact with a side opposite to the circuit side of the semiconductor chip, and a cap enclosing the semiconductor chip and having an opening exposing externally the other end of the heat sink. A metal film is formed at least on the inner wall of the opening and on the surface of the heatsink which is inserted into the cap. An adhesive material is filled between the tip portion of the heat sink and the semiconductor chip, while an adhesive material is filled between the metal films.
In U.S. Pat. No. 5,396,403, there is described a heat sink assembly for a multi-chip module. A thermally conductive plate is bonded to the chips using indium solder. The plate in turn is thermally coupled to a heat sink (cooling) structure (e.g., comprised of finned aluminum) by thermal paste. The plate is made of a material such as silicon carbide or copper-tungsten alloy having a relatively low coefficient of expansion to minimize mechanical stress resulting from lateral motion of the chips due to thermal expansion. Relatively low-power chips may be thermally coupled to the plate by thermal paste instead of being bonded by solder.
In U.S. Pat. No. 5,585,671, there is described a “flip chip” package with a thermally-conductive lid attached to a backside of the chip by a die attach layer of a predetermined thickness range. A rim is formed on the lid with a depth less than a sum of a thickness of the chip, the interconnects, and a minimum final thickness of the die attach layer by a predetermined margin. An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness. An oxide layer, such as an iron or iron-alloy oxide layer, is formed on the bottom surface of the rim. A spacer is placed on the backside of the chip within the die attach material, to define the minimum final thickness of the die attach layer. A beveled or stepped vent hole is formed in the lid and plugged and sealed.
In U.S. Pat. No. 5,621,615, there is described a “flip chip” package comprised of a substrate, a ring structure attached to the substrate, a heat removal structure, and a chip thermally coupled to the heat removal structure. The package lid is comprised of a ring structure and a heat removal structure. The ring structure and heat removal structure are separated until after attachment of the ring structure to the substrate allowing the ring structure to be brazed to the substrate. Brazing the ring structure to the substrate decreases the mechanical stress to the chip. A die attach material between the first major surface of the die and the first major surface of the heat removal structure adheres the die to and thermally couples the die to the heat removal structure. The die attach layer is of a predetermined thickness and thus provides a determined low thermal resistance making the thermal performance of the package certain.
In U.S. Pat. No. 5,710,459, there is described an electronic package which includes a chip cap for covering and protecting an integrated chip therein. The chip cap further forms a concave step near a lower edge of the cap for wrapping around the edge of the package's adapter board for increasing the contact areas between the cap and the board and for attaching the cap to the board. The chip cap is composed of thermal conductive materials and the chip cap further includes a heat sink for dissipating heat generated from the chip. The adapter board further includes a plurality of connecting vias and a plurality of conductive metal balls forming a ball grid array (BGA) underneath the adapter board. The chip is in electrical and thermal contact with the BGA by filling the connection vias with conductive materials. A printed circuit board (PCB) is used for supporting and receiving the adapter board thereon. The PCB includes a plurality of thermal vias penetrating there-through and filled with thermal conductive materials, wherein the thermal vias corresponding to and in contact with a plurality of the conductive metal balls of the BGA are used for dissipating heat generated from the chip.
In U.S. Pat. No. 5,757,620, there is described an apparatus and a method that provides customized cooling of a MCM (Multi-Chip Module) by varying the depth of a thermal compound-filled gap or blind hole above each chip in the module.
In U.S. Pat. No. 5,821,161, there is described a structure and a method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal is a two layer, solder structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder structure has a thick high melting point temperature region that is attached to a cap, and a thin interconnecting region of lower melting point temperature region for sealing the substrate to the cap.
In U.S. Pat. No. 5,825,087, there is described an electronic module with integrated circuit chips mounted on a substrate and having a specially designed cooling plate overlying the chips and producing a gap above same in which a thermal paste or thermal adhesive is positioned. The cooling plate has a roughened area made by grit blasting and the like which penetrates the thermal paste and thermal adhesive and improves the adhesion and inhibits the flow of thermal paste from between the lower surface of the cooling plate and the upper surface of the chip during operation of the electronic module.
In U.S. Pat. No. 5,881,945, there is described a structure and method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. In one embodiment, the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core, and lower melting point thin interconnecting solder layers, where the thin interconnecting solder layers may have similar or different melting points.
In U.S. Pat. No. 5,990,418, there is described a device and method for hermetically sealing an integrated circuit (semiconductor) chip between a substrate and a lid while providing dissipation of heat generated by the integrated circuit chip. The device includes an integrated circuit chip, carrier substrate, interface coolant, and a lid. The chip is attached to the top of the carrier substrate. The interface coolant is disposed on the top of the integrated circuit chip and the lid is placed on top of the carrier substrate/integrated circuit chip combination and contacts the interface coolant. The interface coolant provides a thermal path for conducting heat from the integrated circuit chip to the lid.
In U.S. Pat. No. 6,091,603, there is described an integrated circuit chip packaging module characterized by a customized lid understructure which enables a reduction in the amount of compliant thermally conductive material in the primary heat dissipation path. The lid structure and module are made by processes wherein the lid understructure is customized for the chip(s) to be housed. The customization is achieved by the use of shims and a deformable lid understructure.
In U.S. Pat. No. 6,218,730, tolerances in chip, substrate and hardware dimensions are accommodated by means of a floating sealing structure to insure that compliant thermally conductive paste disposed between the chip and its lid is as trim as possible in order to reduce thermal resistance of the paste so as to be able to run the chip at a cooler temperature. Standoffs are also preferably employed to insure proper paste gap thickness.
In U.S. Pat. No. 6,292,369, there is described an integrated circuit chip package including a customized lid understructure which enables a reduction in the amount of compliant thermally conductive material in the primary heat dissipation path. The lid structure and package are made by processes wherein the lid understructure is customized for the chip(s) to be housed. The customization is achieved by the use of shims and a deformable lid understructure.
In U.S. Pat. No. 6,294,408, there is described an electronic chip assembly which maintains a thin gap spacing between the chip and the lid or heat sink to allow the electronic chip to operate at a relatively cool temperature. Thermal performance is allegedly enhanced by a thermal interface material provided in the thin gap and maintained at a minimal thickness as a result of the structure and assembly process. A thin thermal interface material layer may be achieved with a compression step to compress the thermal interface material before the sealant is cured. In addition, a vent hole is provided in the assembly to prevent pressure build-up inside the package during sealant cure. As the sealant is cured, the gap spacing is maintained, further compression of the thermal interface material is not required, and seal defects are allegedly prevented.
The present invention defines an interposer structure capable of providing effective heat transference there-across while enabling adjustment of the structure's thickness in a relatively facile manner. The structure defined herein is able to provide these advantages while utilizing components which are relatively inexpensive to manufacture and assemble. It is believed that such a structure would represent a significant advancement in the art.